The present invention relates to a frequency synthesizer, and in particular, it relates to a phase noise reduction system of a frequency synthesizer and a method thereof.
As to a prior art example for the frequency synthesizer there is the one disclosed in Japanese Patent Application Laid-Open No. 7-297712. In the disclosed frequency synthesizer, a reference frequency and a number of frequency division of a loop are switched at the same time.
That is to say, initially, it is set such that the reference frequency is large and the number of frequency division of the loop is small, and after a predetermined period of time, it is switched such that the reference frequency becomes small and the number of frequency division of the loop becomes large.
The purpose of initially setting the reference frequency large and the number of frequency division of the loop small is to shorten the time for frequency locking.
Furthermore, the reason of switching such that the reference frequency becomes small and the number of frequency division of the loop becomes large is that if the reference frequency is large, the dissipation current can be increased at a phase comparator.
In such conventional frequency synthesizer, however, since the number of frequency division is switched from small to large when a predetermined period of time passes after the frequency is locked, the number of frequency division has to be kept small for a certain period of time. Under such state where the division number is small, oscillation wave with bad (high) phase noise can be outputted.
Consequently, it has been a problem that it takes long to reach the state where the number of frequency division is large and the phase noise is good (low).
It is therefore, an object of the present invention to provide a phase noise reduction system of a frequency synthesizer and a method thereof, which are capable of switching within a shorter period of time to a state where phase noise is good, thus enabling a high-speed locking.
In accordance with one aspect of the present invention, there is provided a phase noise reduction system of a frequency synthesizer for obtaining an arbitrary frequency oscillation by locking an oscillation frequency of a voltage controlled oscillator to a reference oscillation frequency of a reference oscillator, comprising: a variable frequency divider for voltage controlled oscillator which divides an oscillation frequency of said voltage controlled oscillator; a variable frequency divider for reference oscillator which divides a reference oscillation frequency of said reference oscillator; and a lock detection section which initially sets a common small number of frequency division to said variable frequency divider for voltage controlled oscillator and said variable frequency divider for reference oscillator, respectively, subsequently detects locking of frequency, and switches the setting of number of frequency division from said small number of frequency division to a larger number of frequency division.
Therefore, in this system, the oscillation frequency of the voltage controlled oscillator and the reference oscillation frequency of the reference oscillator are frequency-divided by a smaller number of frequency division, respectively, by which two comparison frequencies are obtained. Then as the system detects that the two comparison frequencies have the same polarity, the number of frequency division is switched from the smaller number of frequency division to the larger number of frequency division. Accordingly, the time during which the phase noise is bad (high) and the number of frequency division is small is shortened.
On the basis of the result of monitoring polarities of both the output signal from the variable frequency divider for voltage controlled oscillator and the output signal from the variable frequency divider for reference oscillator, the lock detection section determines that the frequency is locked when the polarities of both output signals are maintained the same polarity for a predetermined period of time. In accordance with this system, therefore, immediate determination of a frequency lock is possible.
The lock detection section measures the predetermined period of time while taking the output signal from the reference oscillator as a clock signal. In this case, the predetermined period of time is determined giving consideration to shortening of time for switching and preventing false operation.
Furthermore, there is provided an exclusive OR circuit for monitoring polarities of both the output signal from the variable frequency divider for voltage controlled oscillator and the output signal from the variable frequency divider for reference oscillator.
In this system, therefore, immediate detection of frequency lock is made possible.
In accordance with another aspect of the present invention, there is provided a phase noise reduction system of a frequency synthesizer for obtaining an arbitrary frequency oscillation, comprising: a reference oscillator for oscillating a reference oscillation frequency; a voltage controlled oscillator for varying an oscillation frequency by an input DC voltage and locking said oscillation frequency to the reference oscillation frequency of said reference oscillator; a variable frequency divider for voltage controlled oscillator which divides the oscillation frequency of said voltage controlled oscillator; a variable frequency divider for reference oscillator which divides the reference oscillation frequency of said reference oscillator; a phase comparison DC voltage generating section for generating an input DC voltage of said voltage controlled oscillator such that a phase error between a comparison frequency from said variable frequency divider for voltage controlled oscillator and a comparison frequency from said variable frequency divider for reference oscillator becomes small; and a lock detection section which initially sets a common small number of frequency division to said variable frequency divider for voltage controlled oscillator and said variable frequency divider for reference oscillator, respectively, subsequently detects locking of frequency, and switches the setting of number of frequency division from said small number of frequency division to a larger number of frequency division.
In accordance with the present invention, therefore, two comparison frequencies are obtained as the oscillation frequency from the voltage controlled oscillator and the reference oscillation frequency from the reference oscillator are divided by the smaller number of frequency division. Then as it is detected that the polarities of the comparison frequencies have become the same, the number of frequency division is switched from the smaller one to the larger one. Consequently, the time in which the number of frequency division is small and the phase noise is bad (high) is shortened.
In accordance with still another aspect of the present invention, there is provided a phase noise reduction method of a frequency synthesizer for obtaining an arbitrary frequency oscillation by locking an oscillation frequency of a voltage controlled oscillator to a reference oscillation frequency of a reference oscillator, comprising the steps of: initially frequency-dividing the oscillation frequency of said voltage controlled oscillator and the reference oscillation frequency of said reference oscillator, respectively, by a common small number of frequency division; detecting a lock of said frequency being frequency-divided; and after detecting the lock of said frequency, switching the frequency division by said small number of frequency division to the frequency division by a larger number of frequency division.
Likewise, in accordance with the present invention, two comparison frequencies are obtained as the oscillation frequency from the voltage controlled oscillator and the reference oscillation frequency from the reference oscillator are divided by the smaller number of frequency division. Then as it is detected that the polarities of the comparison frequencies have become the same, the number of frequency division is switched from the smaller one to the larger one. Consequently, the time in which the number of frequency division is small and the phase noise is bad (high) is shortened.